View DS2760AE-025_8689913.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 25 010906 features li+ safety circuit - overvoltage protection - overcurrent/short circuit protection - undervoltage protection zero volt battery recovery charge available in two configurations: - internal 25m sense resistor - external user-selec table sense resistor current measurement - 12-bit bidirectional measurement - internal sense resistor configuration: 0.625ma lsb and 1.9a dynamic range - external sense resistor configuration: 15.625 v lsb and 64mv dynamic range current accumulation - internal sense resistor: 0.25mahr lsb - external sense resistor: 6.25 vhr lsb voltage measurement with 4.88mv resolution temperature measurement using integrated sensor with 0.125 c resolution system power management and control feature support 32 bytes of lockable eeprom 16 bytes of general purpose sram dallas 1-wire ? interface with unique 64-bit device address low power consumption: - active current: 90 a max - sleep current: 2 a max pin assignment pin description cc - charge control output dc - discharge control output dq - data input/output pio - programmable i/o pin pls - battery pack positive terminal input ps - power switch sense input vin - voltage sense input v dd - power supply input (2.5v to 5.5v) vss - device ground sns - sense resistor connection is1 - current sense input is2 - current sense input sns probe - do not connect vss probe - do not connect ds2760 high-precision li+ battery monito r www.maxim-ic.com cc vin v dd pio vss vss vss ps is1 ds2760 16-pin tssop package is2 sns sns 1 2 2 3 2 1 4 5 6 7 8 1615 14 13 12 11 10 9 sns dq pls dc ds2760 flip-chip packaging top view 1-wire is a registered trademark of dallas semiconductor. pls dc dq cc is2 vin is1 vdd pio ps sns vss 1 2 3 4 ab c d e f sns probe vss probe downloaded from: http:///
ds2760 2 ordering information part marking description ds2760ae+ ds2760a tssop, external sense resistor, 4.275v vov, lead-free ds2760be+ ds2760b tssop, external sense resistor, 4.35v vov, lead-free ds2760ae+t&r ds2760a ds2760ae+ on tape & reel, lead-free ds2760 be+t&r ds2760b ds2760be+ on tape & reel, lead-free ds2760ae+025 2760a25 tssop, 25m sense resistor, 4.275v vov, lead-free ds2760be+025 2760b25 tssop, 25m sense resistor, 4.35v vov, lead-free ds2760ae+025/t&r 2760a25 ds2760ae+025 in tape & reel, lead-free ds2760be+025/t&r 2760b25 ds2760be+025 in tape & reel, lead-free ds2760ax ds2760a flipchip, external sense resi stor, tape & reel, 4.275v vov ds2760bx ds2760b flipchip, external sense resi stor, tape & reel, 4.35v vov ds2760ax-025 ds2760ar flipchip, 25m sense resistor, tape & reel, 4.275v vov ds2760bx-025 ds2760br flipchip, 25m sense resistor, tape & reel, 4.35v vov ds2760ae ds2760a tssop, external sense resistor, 4.275v vov ds2760be ds2760b tssop, external sense resistor, 4.35v vov ds2760ae/t&r ds2760a ds2760ae on tape & reel ds2760 be/t&r ds2760b ds2760be on tape & reel DS2760AE-025 2760a25 tssop, 25m sense resistor, 4.275v vov ds2760be-025 2760b25 tssop, 25m sense resistor, 4.35v vov DS2760AE-025/t&r 2760a25 DS2760AE-025 in tape & reel ds2760be-025/t&r 2760b25 ds2760be-025 in tape & reel description the ds2760 high-precision li+ battery monitor is a da ta acquisition, informati on storage, and safety protection device tailored for cost-sensitive battery pack applications. this low-power device integrates precise temperature, voltage, and current measuremen t, nonvolatile data storage, and li+ protection into the small footprint of either a tssop package or flip chip. the ds2760 is a key component in applications including remaining capacity estimation, sa fety monitoring, and battery -specific data storage. via its 1-wire interface, the ds2760 gives the host system read/write access to status and control registers, instrumentation registers, and general pur pose data storage. each device has a unique factory- programmed 64-bit net address whic h allows it to be individually addressed by the host system, supporting multi-ba ttery operation. the ds2760 is capable of performing temperature, voltage and current measurement to a resolution sufficient to support process monitoring applications su ch as battery charge control, remaining capacity estimation, and safety monitoring. temperature is meas ured using an on-chip sensor, eliminating the need for a separate thermistor. bidirectional current measurement and accumulation are accomplished using either an internal 25m sense resistor or an external device. the ds2760 also features a programmable i/o pin that allows the host system to sense and cont rol other electronics in the pack, including switches, vibration motors, speakers and leds. three types of memory are provided on the ds2760 fo r battery information storage: eeprom, lockable eeprom and sram. eeprom memory saves important battery data in true nonvol atile memory that is unaffected by severe battery depletion, accidental shorts or esd events. lockable eeprom becomes rom when locked to provide additional security for unchanging battery data. sram provides inexpensive storage for temporary data. downloaded from: http:///
ds2760 3 block diagram figure 1 1-wire interface and address thermal sense mux voltage reference adc registers and user memory 25m dq chi p g round + - lockable eeprom sram temperature voltage current accum. current status / control li+ protection vin is1is2 sns is2 is1 vss ccdc pls ps pio timebase internal sense resistor configuration only downloaded from: http:///
ds2760 4 detailed pin description table 1 symbol tssop* flip chip* description cc 1 c1 charge protection control output. controls an external p-channel high-side charge protection fet. dc 3 b2 discharge protection control output. controls an external p-channel high-side discharge protection fet. dq 7 b4 data input/out. 1-wire data line. open-drain output driver. connect this pin to the data terminal of the battery pack. pin has an internal 1 a pull-down for sensing disconnection. pio 14 e2 programmable i/o pin. used to control and monitor user-defined external circuitry. open drain to vss. pls 2 b1 battery pack positive terminal input. the device monitors the state of the battery packs positive terminal through this pin in order to detect events such as the attachment of a charger or the removal of a short circuit. additionally, a charge path to recover a deeply depleted cell is provided from pls to vdd. ps 10 e4 power switch sense input. the device wakes up from sleep mode when it senses the closure of a switch to vss on this pin. pin has an internal 1 a pull-up to v dd . vin 16 d1 voltage sense input. the voltage of the li+ cell is monitored via this input pin. this pin has a weak pullup to v dd . v dd 15 e1 power supply input. connect to the positive terminal of the li+ cell through a decoupling network. vss 11,12,13 f3 device ground. connect directly to the negative terminal of the li+ cell. for the external sense resistor conf iguration, connect the sense resistor between vss and sns. sns 4,5,6 a3 sense resistor connection. connect to the negative terminal of the battery pack. in the internal sense resi stor configuration, the sense resistor is connected between vss and sns. is1 9 d4 current sense input. this pin is internally connected to vss through a 4.7k resistor. connect a 0.1 f capacitor between is1 and is2 to complete a low-pass input filter. is2 8 c4 current sense input. this pin is internally connected to sns through a 4.7k resistor. sns probe n/a c2 do not connect. vss probe n/a d2 do not connect. * mechanical drawing for the 16-pin tssop and ds2760 flip-chip package can be found at: http://pdfserv.maxim-ic.co m/arpdf/packages/16tssop.pdf http://pdfserv.maxim-ic.com/a rpdf/packages/chips/2760x.pdf downloaded from: http:///
ds2760 5 application example figure 2 1 C r sens is present for external sense resistor configurations only 2 C r sensint is present for internal sense resistor configurations only sns ds2760 vss is2 is1 4.7k 4.7k voltage sense r sensint (2) r ks r ks pack+ pack- dat a 150 150 1k 150 1k 1k ds2760 104 cc pls dc sns sns sns dq is2 vin v dd pio vss vss vss ps is1 102 104 1 0 2 bat+ bat- r sens (1) 4.7k ps downloaded from: http:///
ds2760 6 power modes the ds2760 has two power modes: active and sleep. while in ac tive mode, the ds2760 continually measures current, voltage and temperature to provi de data to the host system and to support current accumulation and li+ safety monitoring. in sleep mode, the ds2760 ceases these activities. the ds2760 enters sleep mode when any of the following conditions occurs: the pmod bit in the status register has been set to 1 and the dq line is low for longer than 2 seconds (pack disconnection) the voltage on vin drops below undervoltage threshold v uv for t uvd (cell depletion) the pack is disabled through the issuance of a swap command (swen bit =1) the ds2760 returns to active mode when any of the following occurs: the pmod bit has been set to 1 and the swen bit is set to 0 and the dq line is pulled high (pack connection) the ps pin is pulled low (power switch) the voltage on pls becomes greater than the voltage on vin (charger connection) with the swen bit set to 0 the pack is enabled through the issuance of a swap command (swen bit =1) the ds2760 defaults to sleep mode when power is first applied. li+ protection circuitry during active mode, the ds2760 constantly monitors ce ll voltage and current to protect the battery from overcharge (overvoltage), overdischarge (undervolta ge) and excessive charge and discharge currents (overcurrent, short circuit). cond itions and ds2760 responses are described in the sections below and summarized in table 2 and figure 3. li+ protection conditions and ds2760 responses table 2 activation condition name threshold delay response release threshold overvoltage vin > v ov t ovd cc high vin < v ce undervoltage vin < v uv t uvd cc , dc high, sleep mode v pls > v dd (1) (charger connected) overcurrent, charge v is > v oc (2) t ocd cc , dc high v pls < v dd C v tp (3) overcurrent, discharge v is < -v oc (2) t ocd dc high v pls > v dd C v tp (4) short circuit v sns > v sc t scd dc high v pls > v dd C v tp (4) v is = v is1 C v is2 . logic high = v pls for cc and v dd for dc . all voltages are with respect to vss. i sns references current delivered from pin sns. (1) if v dd <2.2v, release is delayed until the recovery charge current (i rc ) passed from pls to v dd charges the battery and allows v dd to exceed 2.2v. (2) for the internal sense resistor configuration, th e overcurrent thresholds are expressed in terms of current: i sns > i oc for charge direction and i sns < -i oc for discharge direction (3) with test current i tst current flowing from pls to vss (pull-down on pls) (4) with test current i tst current flowing from v dd to pls (pull-up on pls) overvoltage. if the voltage of the cell exceeds overvoltage threshold v ov for a period longer than overvoltage delay t ovd , the ds2760 shuts off the external char ge fet and sets the ov flag in the protection register. when the cell voltage falls below charge enable threshold v ce , the ds2760 turns the downloaded from: http:///
ds2760 7 charge fet back on (unless another protection cond ition prevents it). discharging remains enabled during overvoltage. undervoltage. if the voltage of the cell drops below undervoltage threshold v uv for a period longer than undervoltage delay t uvd , the ds2760 shuts off the charge and discharge fets, sets the uv flag in the protection register, and enters sleep m ode. the ds2760 provides a current-limited (i rc ) recovery charge path from pls to vdd to gently charge severely depleted cells. the recovery path is enable d when 0 vdd < 3v(typ). once vdd reaches 3v(typ), the ds2760 will return to normal operation, awaiting connection of a charger to turn on th e charge fet and pull out of sleep mode. overcurrent, charge direction. the voltage difference between the is1 pin and the is2 pin (v is = v is1 C v is2 ) is the filtered voltage drop across the current sense resistor. if v is exceeds overcurrent threshold v oc for a period longer than overcurrent delay t ocd , the ds2760 shuts off both external fets and sets the coc flag in the protection register. the charge current path is not re-established until the voltage on the pls pin drops below v dd C v tp . the ds2760 provides a test current of value i tst from pls to vss to pull pls down in order to detect the remova l of the offending charge current source. overcurrent, discharge direction. if v is is less than Cv oc for a period longer than t ocd , the ds2760 shuts off the external discharge fet and sets the doc flag in the protection register. the discharge current path is not re-established until the voltage on pls rises above v dd C v tp . the ds2760 provides a test current of value i tst from v dd to pls to pull pls up in order to detect the removal of the offending low-impedance load. short circuit. if the voltage on the sns pin with respect to vss exceeds short circuit threshold v sc for a period longer than short circuit delay t scd , the ds2760 shuts off the external discharge fet and sets the doc flag in the protection register. the discharge current path is not re-established until the voltage on pls rises above v dd C v tp . the ds2760 provides a test current of value i tst from v dd to pls to pull pls up in order to detect the re moval of the short circuit. lithium-ion protection circuitry example waveforms figure 3 (1) to allow the device to react quickly to short circ uits, detection is actually done on the sns pin rather than on the filtered is1 and is2 pins. the actual short circuit detect condition is v sns > v sc . sleep mode v ov v ce v uv v cell v is charge discharge ccdc -v sc v oc -v oc 0 t scd t ocd t ocd t uvd t ovd v pls vdd active vss vss inactive t ovd (1) downloaded from: http:///
ds2760 8 summary. all of the protection conditi ons described above are ored together to affect the cc and dc outputs. dc = (undervoltage) or (overcurrent, eith er direction) or (short circuit) or (protection register bit de = 0) or (sleep mode) cc = (overvoltage) or (undervoltage) or (overcurre nt, charge direction) or (protection register bit ce = 0) or (sleep mode) current measurement in the active mode of operation, the ds2760 continuall y measures the current flow into and out of the battery by measuring the voltage drop across a curre nt sense resistor. the ds2760 is available in two configurations: (1) internal 25m current sense resistor, and (2) extern al user-selectable sense resistor. in either configuration, the ds2760 considers the vo ltage difference between pins is1 and is2 (v is = v is1 C v is2 ) to be the filtered voltage drop across the sense resistor. a positive v is value indicates current is flowing into the battery (charging), while a negative v is value indicates current is flowing out of the battery (discharging). v is is measured with a signed resolution of 12-bits. the current register is upda ted in twos complement format every 88ms (128/fsample) with an average of 128 readings. currents outside the range of the register are reported at the limit of the range. the format of the current register is shown in figure 4. for the internal sense resistor configuration, the ds 2760 maintains the current register in units of amps, with a resolution of 0.625ma and full scale range of no less than 1.9a (see note 7 on i fs spec for more details). the ds2760 automatically compensates for internal sense resistor process variations and temperature effects when reporting current. for the external sense resistor config uration, the ds2760 writes the measured v is voltage to the current register, with a resolution of 15.625 v and a full scale range of 64mv. current register format figure 4 msbaddress 0e lsbaddress 0f s 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x m s b l s b m s b l s b units: 0.625 ma for internal sense resistor 15.625 v for external sense resistor current accumulator the current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the battery. current flow into the battery increments the current accumulator while current flow out of the battery decrements it. data is maintained in the current accumulator in twos- complement format. the format of the current accumulator is shown in figure 5. when the internal sense resistor is used, the ds2760 maintains the current accumulator in units of amp- hours, with a resolution of 0.25mahrs and full scale range of 8.2ahrs. when using an external sense downloaded from: http:///
ds2760 9 resistor, the ds2760 maintains the current accumulato r in units of volt-hours, with a resolution of 6.25 vhrs and a full scale range of 205 mvhrs. the current accumulator is a read/write register that can be altered by the host system as needed. current accumulator format figure 5 msbaddress 10 lsbaddress 11 s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 m s b l s b m s b l s b units: 0.25 mahrs for internal sense resistor 6.25 vhrs for external sense resistor current offset compensation current measurement and the current accumulation are both internally compensated for offset on a continual basis minimizing error resulting from variations in device temperature and voltage. additionally a constant bias may be utilized to alter any other sources of offset. this bias resides in eeprom address 33h in twos- complement format and is subtract ed from each current measurement. the current offset bias is applied to both the intern al and external sense resi stor configurations. the factory default for the current offset compensation is a value of 0. current offset bias figure 6 address 33 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 m s b l s b units: 0.625 ma for internal sense resistor 15.625 v for external sense resistor voltage measurement the ds2760 continually measures the voltage between pins vin and vss over a range of 0 to 4.75v. the resulting data is placed in the voltage register in twos-complement format with a resolution of 4.88mv. voltages above the maximum register value are reported as the maximum value. the voltage register format is shown in figure 7. voltage register format figure 7 msbaddress 0c lsbaddress 0d s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x m s b l s b m s b l s b units: 4.88 mv downloaded from: http:///
ds2760 10 temperature measurement the ds2760 uses an integrated te mperature sensor to continuall y measure battery temperature. temperature measurements are placed in the temperature register in twos-complement format with a resolution of 0.125c over a range of 127c. the temperature register format is shown in figure 8. temperature register format figure 8 msbaddress 18 lsbaddress 19 s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x m s b l s b m s b l s b units: 0.125 c programmable i/o to use the pio pin as an output, write the desired output value to the pio bit in the special feature register. writing a 0 to the pio bit enables the pio output driver, pulling the pio pin to vss. writing a 1 to the pio bit disables the output driver, allowing the pio pin to be pulled high or used as an input. to sense the value on the pio pin, read the pio bit. the ds2760 turns off the pio output driver and sets the pio high when it enters sleep mode or when dq is low for more than 2 seconds, regardless of the state of the pmod bit. power switch input the ds2760 provides a power control function that uses the discharge protection fet to gate battery power to the system. the ps pin, internally pulled to v dd through a 1 a current source, is continuously monitored for a low-impedance connection to vss. if the ds2760 is in sleep mode, the detection of a low on ps causes the device to transition into active mode, turning on the discharge fet. if the ds2760 is already in active mode, activity on ps has no effect other than the mirroring of its logic level in the ps bit in the special feature register. the reading of a 0 in the ps bit should be immediately followed by writing a 1 to the ps bit to ensure proper operation. memory the ds2760 has a 256-byte linear address space with regi sters for instrumentation, status and control in the lower 32 bytes, with lockable eeprom and sram memory occupying portions of the remaining address space. all eeprom and sram memory is general-purpose except addresses 30h, 31h, and 33h, which should be written with the defa ult values for the protection regist er, status register, and current offset register, respectively. when the msb of any 2-byte register is read, both the msb and lsb are latched and held for the duration of the read data command to prevent updates during the read and ensure synchronization between the two register bytes. for consistent results, always read the msb a nd the lsb of a two-byte register during the same read data command sequence. eeprom memory is shadowed by ram to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to eeprom. all reads and writes to/from eeprom memory actually access the shadow ram. in unlocked eeprom blocks, the write data command updates shadow ram. in locked eeprom bl ocks, the write data command is ignored. the copy data command copies the contents of sh adow ram to eeprom in an unlocked block of eeprom but has no effect on locked blocks. the recall data command copies the contents of a block of eeprom to shadow ram regardless of whether the block is locked or not. downloaded from: http:///
ds2760 11 memory map table 3 address (hex) description read/write 00 protection register r/w 01 status register r 02-06 reserved 07 eeprom register r/w 08 special feature register r/w 09-0b reserved 0c voltage register msb r 0d voltage register lsb r 0e current register msb r 0f current register lsb r 10 accumulated current register msb r/w 11 accumulated current register lsb r/w 12-17 reserved 18 temperature register msb r 19 temperature register lsb r 1a-1f reserved 20-2f eeprom, block 0 r/w* 30-3f eeprom, block 1 r/w* 40-7f reserved 80-8f sram r/w 90-ff reserved * each eeprom block is read/write until locked by the lock command, after which it is read-only. protection register the protection register consists of flags that indi cate protection circuit status and switches that give conditional control over the charging and discharging paths. bits ov, uv, coc and doc are set when corresponding protection conditions occur and remain set until cleared by the host system. the default values of the ce and de bits of the protection register are stored in lockable eeprom in the corresponding bits in address 30h. a recall data command for eeprom block 1 recalls the default values of 1 into ce and de. the format of the prot ection register is shown in figure 9. the function of each bit is described in detail in the following paragraphs. protection register format figure 9 address 00 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ov uv coc doc cc dc ce de ov C overvoltage flag. when set to 1, this bit indicates the battery pack has experienced an overvoltage condition. this bit must be reset by the host system. uv C undervoltage flag. when set to 1, this bit indicates the battery pack has experienced an undervoltage condition. this bit mu st be reset by the host system. downloaded from: http:///
ds2760 12 coc C charge overcurrent flag. when set to 1, this bit indicates the battery pack has experienced a charge-direction overcurrent condition. this bit must be reset by the host system. doc C discharge overcurrent flag. when set to 1, this bit indicates the battery pack has experienced a discharge-direction overcurrent condition. this bit must be reset by the host system. cc C cc pin mirror. this read-only bit mirrors the state of the cc output pin. dc C dc pin mirror. this read-only bit mirrors the state of the dc output pin. ce C charge enable. writing a 0 to this bit disables charging ( cc output high, external charge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables charging, subject to override by the presence of any protection conditions. the ds2760 automatically sets this bit to 1 when it transitions from sleep mode to active mode. de C discharge enable. writing a 0 to this bit disables discharging ( dc output high, external discharge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables discharging, subject to override by the presence of any protection conditions. the ds2760 automatically sets this bit to 1 when it transitions from sleep mode to active mode. status register the default values for the status register bits are stored in lockable eeprom in the corresponding bits of address 31h. a recall data command for eeprom bl ock 1 recalls the default values into the status register bits. the format of the status register is shown in figure 10. the function of each bit is described in detail in the following paragraphs. status register format figure 10 address 01 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 x x pmod rnaop swen x x x pmod C sleep mode enable. a value of 1 in this bit enables the ds2760 to enter sleep mode when the dq line goes low for greater than 2 seconds and leav e sleep mode when the dq line goes high. a value of 0 disables dq-related transitions into and out of sleep mode. this bit is read-only. the desired default value should be set in bit 5 of address 31h. the factory default is 0. rnaop C read net address opcode. a value of 0 in this bit sets the opcode for the read net address command to 33h, while a 1 sets the opcode to 39h. this bit is read-only. the desired default value should be set in bit 4 of address 31h. the factory default is 0. swen - swap command enable. a value of 1 in this bit location enables the recognition of a swap command. if set to 0, swap commands are ignored. th e desired default value should be set in bit 3 of address 31h. this bit is read-onl y. the factory default is 0. x C reserved bits. downloaded from: http:///
ds2760 13 eeprom register the format of the eeprom register is shown in figure 11. the function of each bit is described in detail in the following paragraphs. eeprom register format figure 11 address 07 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 eec lock x x x x bl1 bl0 eec C eeprom copy flag. a 1 in this read-only bit indicates that a copy data command is in progress. while this bit is high, writes to eeprom addresses are ignored. a 0 in this bit indicates that data may be written to unlocked eeprom blocks. lock C eeprom lock enable. when this bit is 0, the lock command is ignored. writing a 1 to this bit enables the lock command. after the lock command is executed, the lock bit is reset to 0. the factory default is 0. bl1 C eeprom block 1 lock flag. a 1 in this read-only bit indicates that eeprom block 1 (addresses 30-3f) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). bl0 C eeprom block 0 lock flag. a 1 in this read-only bit indicates that eeprom block 0 (addresses 20-2f) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write). x C reserved bits. special feature register the format of the special feature register is shown in figure 12. the function of each bit is described in detail in the following paragraphs. special feature register format figure 12 address 08 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ps pio mstr x x x x x ps C ps pin mirror. this read-only bit mirrors the stat e of the ps pin. the reading of a 0 in this bit should be immediately followed by writing a 1 to this location to insure proper operation. pio C pio pin sense and control. see the programmable i/o section for details on this read/write bit. mstr - swap master status bit. this bit indicates whether a device has been selected through the swap command. selection of this device through the swap command and the appropriate net address will result in setting this bit, indicating that this devi ce is the master. a 0 signifies that this device is not the master. x C reserved bits. downloaded from: http:///
ds2760 14 1-wire bus system the 1-wire bus is a system which has a single bus master and one or more slaves. a multidrop bus is a 1-wire bus with multiple slaves. a single-drop bus has only one slave device. in all instances, the ds2760 is a slave device. the bus master is typi cally a microprocessor in the host system. the discussion of this bus system consists of four t opics: 64-bit net address, hardware configuration, transaction sequence, a nd 1-wire signaling. 64-bit net address each ds2760 has a unique, factory-prog rammed 1-wire net addre ss which is 64 bits in length. the first 8 bits are the 1-wire family code (30h for ds2760). the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits (see figure 13). the 64-bit net address and the 1-wire i/o circuitry built into the device enable the ds2760 to communicate via the 1-wire protocol detailed in the 1-wire bus system section of this data sheet. 1-wire net address format figure 13 8-bit crc 48-bit serial number 8-bit family code 30h) msb lsb crc generation the ds2760 has an 8-bit crc stored in the most signific ant byte of its 1-wire ne t address. to ensure error-free transmission of the address, the host system can compute a crc value from the first 56 bits of the address and compare it to the crc from the ds2760. the host system is responsible for verifying the crc value and taking action as a result. th e ds2760 does not compare crc values and does not prevent a command sequence from proceeding as a result of a crc mismatch. proper use of the crc can result in a communication channel with a very high level of integrity. the crc can be generated by the host using a circuit consisting of a shift register and xor gates as shown in figure 10, or it can be generated in soft ware. additional information about the dallas 1-wire cyclic redundancy check is available in application note 27 entitled understanding and using cyclic redundancy checks with dallas semi conductor touch memory products . (this application note can be found on the maxim/dallas semiconducto r website at www.maxim-ic.com). in the circuit in figure 14, the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. downloaded from: http:///
ds2760 15 1-wire crc generation block diagram figure 14 hardware configuration because the 1-wire bus has only a single line, it is important that each device on the bus be able to drive it at the appropriate time. to fac ilitate this, each device attached to the 1-wire bus must connect to the bus with open-drain or tri-state out put drivers. the ds2760 used an ope n-drain output driver as part of the bidirectional interface circuitry shown in figure 15. if a bidirectional pin is not available on the bus master, separate output and input pins can be tied together. the 1-wire bus must have a pull-up resistor at the bus -master end of the bus. for short line lengths, the value of this resistor should be approximately 5k . the idle state for the 1-wire bus is high. if, for any reason, a bus transaction must be suspended, the bus mu st be left in the idle state in order to properly resume the transaction later. if the bus is left low for more than 120 s, slave devices on the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction. 1-wire bus interface circuitry figure 15 transaction sequence the protocol for accessing the ds2760 via the 1-wire port is as follows: initialization net address command function command transaction/data the sections that follow describe each of these steps in detail. 1 a typ. 100 mosfet tx rx rx tx rx = receive tx = transmit +v pullup (2.0vC5.5v) 4.7k bus master ds2760 1-wire port msb xor xor lsb xor in p ut downloaded from: http:///
ds2760 16 all transactions of the 1-wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master followed by a presence pulse simultaneously transmitted by the ds2760 and any other slaves on the bus. the presence pulse tells the bus master that one or more devices are on the bus and ready to operate. for more details, see the 1-wire signaling section. net address commands once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. the name of each rom command is followed by the 8-bit opcode for that command in squa re brackets. figure 16 presents a transaction flowchart of the net address commands. read net address [33h or 39h]. this command allows the bus mast er to read the ds2760s 1-wire net address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves tr y to transmit at the same time (open-drain produces a wired-and result). the rnaop bit in the status register selects the opcode for this command, with rnaop=0 indicating 33h and rnaop=1 indicating 39h. match net address [55h]. this command allows the bus master to specifically address one ds2760 on the 1-wire bus. only the addressed ds2760 responds to any subsequent function command. all other slave devices ignore the function command and wait for a reset pulse. this command can be used with one or more slave devices on the bus. skip net address [cch]. this command saves time when there is only one ds2760 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. if more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. search net address [f0h]. this command allows the bus master to use a process of elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one device. the remaining devices can then be id entified on additional iterations of th e process. see chapter 5 of the book of ds19xx i button ? standards for a comprehensive discussion of a net address search, including an actual example. (this publica tion can be found on the maxim/da llas semiconductor website at www.maxim-ic.com). swap [aah]. swap is a net address level command speci fically intended to aid in distributed multiplexing applications and is described specifically with regards to power control using the 27xx series of products. the term power control refers to the ab ility of the ds2760 to control the flow of power into or out the battery pack using control pins dc and cc . the swap command is issued followed by the net address. the effect is to cause the addressed device to enable power to or from the system while simultaneously (break-before-make ) deselecting and powering down (sleep) all other packs. this switching sequence is controlled by a timing pulse issued on the dq line following the net address. the falling edge of the pulse is used to disable power with the rising edge enabling power flow by the selected device. the ds2760 will recognize a swap command, devi ce address, and timing pulse if and only if the swen bit is set. i button is a registered trademark of dallas semiconductor. downloaded from: http:///
ds2760 17 function commands after successfully completing one of the net address commands, the bus master can access the features of the ds2760 with any of the function commands described in the following paragraphs. the name of each function is followed by the 8-bit opcode for that command in square brackets. read data [69h, xx]. this command reads data from the ds2760 starting at memory address xx. the lsb of the data in address xx is available to be r ead immediately after the msb of the address has been entered. because the address is automatically incremented after the msb of each byte is received, the lsb of the data at address xx+1 is available to be read immediately after the msb of the data at address xx. if the bus master continues to read beyond address ffh, the ds2760 outputs logic 1 until a reset pulse occurs. addresses labeled reserved in the memory map contain undefine d data. the read data command may be terminated by the bus mast er with a reset pulse at any bit boundary. write data [6 ch, xx]. this command writes data to the ds2760 starting at memory address xx. the lsb of the data to be stored at address xx can be written immediately after the msb of address has been entered. because the address is auto matically incremented after the msb of each byte is written, the lsb to be stored at address xx+1 can be written immediately after the msb to be stored at address xx. if the bus master continues to write be yond address ffh, the ds2760 ignores the data. writes to read-only addresses, reserved addresses and locked eeprom blocks are ignored. incomplete bytes are not written. writes to unlocked eeprom bloc ks are to shadow ram rather than eeprom. see the memory section for more details. copy data [48h, xx]. this command copies the contents of shadow ram to eeprom for the 16-byte eeprom block containing address xx . copy data commands that addre ss locked blocks are ignored. while the copy data command is executing, the eec bit in the eeprom register is set to 1 and writes to eeprom addresses are ignored. reads and wr ites to non-eeprom addresses can still occur while the copy is in progress. the copy data command takes t eec time to execute, starting on the next falling edge after the address is transmitted. recall data [b8h, xx]. this command recalls the contents of the 16-byte eeprom block containing address xx to shadow ram. lock [6 ah, xx]. this command locks (write-protects) the 16-byte block of eeprom memory containing memory address xx. the lock bit in the eeprom register must be set to l before the lock command is executed. if the lock bit is 0, the lock command has no effect. the lock command is permanent; a locked block can never be written again. downloaded from: http:///
ds2760 18 function commands table 4 command description command protocol bus state after command protocol bus data read data reads data from memory starting at address xx 69h, xx master rx up to 256 bytes of data write data writes data to memory starting at address xx 6ch, xx master tx up to 256 bytes of data copy data copies shadow ram data to eeprom block containing address xx 48h, xx bus idle none recall data recalls eeprom block containing address xx to shadow ram b8h, xx bus idle none lock permanently locks the block of eeprom containing address xx 6ah, xx bus idle none downloaded from: http:///
ds2760 19 net address command flow chart figure 16 master tx reset pulse ds2760 tx presence pulse master tx net address command 55h match 33h / 39h read f0h search cch skip ds2760 tx family code 1 byte ds2760 tx serial number 6 bytes ds2760 tx crc 1 byte master tx bit 0 bit 0 match ? master tx bit 1 ds2760 tx bit 0 ds2760 tx bit 0 master tx bit 0 bit 0 match ? ds2760 tx bit 1 ds2760 tx bit 1 master tx bit 1 bit 1 match ? bit 1 match ? master tx function command master tx bit 63 ds2760 tx bit 63 ds2760 tx bit 63 master tx bit 63 bit 63 match ? master tx function command yes no no no no yes yes yes no no no no yes yes yes yes no yes aah swap no yes master tx bit 0 bit 0 match ? master tx bit 1 bit 1 match ? master tx bit 63 bit 63 match ? no yes yes no yes no ds2760 to sleep mode falling edge of dq ds2760 to active mode rising edge of dq downloaded from: http:///
ds2760 20 i/o signaling the 1-wire bus requires strict signaling protocols to insu re data integrity. the four protocols used by the ds2760 are: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. all of these types of signaling except the presence pulse are initiated by the bus master. the initialization sequence required to begin any comm unication with the ds2760 is shown in figure 17. a presence pulse following a reset pulse indicat es the ds2760 is read to accept a net address command. the bus master transmits (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line is then pulled high by the pull-up resistor. after detecting the rising edge on th e dq pin, the ds2760 waits for t pdh and then transmits the presence pulse for t pdl . 1-wire initialization sequence figure 17 write time slots a write time slot is initiated when the bus master pulls the 1-wire bus from a logic high (inactive) level to a logic low level. there are two types of write time slots: write 1 and write 0. all write time slots must be t slot (60 s to 120 s) in duration with a 1 s minimum recovery time, t rec , between cycles. the ds2760 samples the 1-wire bus line between 15 s and 60 s after the line falls. if the line is high when sampled, a write 1 occurs. if the line is low when sampled, a write 0 occurs (see figure 18). for the bus master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high within 15 s after the start of the write time slot. for the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the write time slot. read time slots a read time slot is initiated when the bus master pulls the 1-wire bus line from a logic high level to a logic low level. the bus master must keep the bus line low for at least 1 s and then release it to allow the ds2760 to present valid data. the bus master can then sample the data t rdv (15 s) from the start of the read time slot. by the end of the read time slot, the ds2760 releases the bus line and allows it to be pulled high by the external pull-up resi stor. all read time slots must be t slot (60 s to 120 s) in duration with a 1 s minimum recovery time, t rec , between cycles. see figure 18 for more information. t r s tl t pdl t r s th t pdh pack+ packC line type legend: bus master active low ds2760 active low resistor pullup both bus master and ds2760 active low dq downloaded from: http:///
ds2760 21 1-wire write and read time slots figure 18 swap command timing figure 19 pack+ packC t s l o t dq t low1 t s l o t write 0 slot write 1 slot t low0 t re c >1 s ds2760 sample window min typ max 15 s 15 s 30 s ds2760 sample window min typ max 15 s 15 s 30 s line type legend: bus master active low ds2760 active low res istor pullup both bus master and ds2760 active low t s l o t read 0 slot read 1 slot t slot t rec >1 s t rdv master sample window master sample window t rdv pack+ packC dq t swoff t swon t swl cc , dc cc , dc dq downloaded from: http:///
ds2760 22 absolute maximum ratings* voltage on pls and cc pin, relative to vss -0.3v to +18v voltage on pio pin, relative to vss -0.3v to +12v voltage on vin and ps , relative to vss -0.3v to v dd + 0.3 voltage on any other pin, relative to vss -0.3v to +6v continuous internal sense resistor current 2.5a pulsed internal sense resistor current 50a for <100s/sec, <1000 pulses operating temperature rang e -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020a specification * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-20 c to +70 c, 2.5v v dd 5.5v) parameter symbol condition min typ max units notes supply voltage v dd 2.5 5.5 v 1 data pin dq -0.3 5.5 v 1 dc electrical characteristics (-20 c to +70 c; 2.5v v dd 5.5v) parameter symbol condition min typ max units notes active current i active dq = v dd , norm. operation 60 90 a sleep mode current i sleep dq = 0v, no activity, ps floating 1 2 a input logic high: dq, pio v ih 1.5 v 1 input logic high: ps v ih v dd - 0.2v v 1 input logic low: dq, pio v il 0.4 v 1 input logic low: ps v il 0.2 v 1 output logic high: cc v oh i oh = -0.1ma v pls - 0.4v v 1 output logic high: dc v oh i oh = -0.1ma v dd - 0.4v v 1 output logic low: cc , dc v ol i ol = 0.1ma 0.4 v 1 output logic low: dq, pio v ol i ol = 4ma 0.4 v 1 dq pulldown current i pd 1 a input resistance: vin r in 5 m internal current sense resistor r sns +25 c 20 25 30 m dq low to sleep time t sleep 2.1 sec downloaded from: http:///
ds2760 23 electrical characteristics: protection circuitry (0 c to +50 c; 2.5v v dd 5.5v) parameter symbol min typ max units notes overvoltage detect v ov 4.325 4.250 4.350 4.275 4.375 4.300 v 1, 2 charge enable v ce 4.10 4.15 4.20 v 1 undervoltage detect v uv 2.5 2.6 2.7 v 1 overcurrent detect i oc 1.8 1.9 2.0 a 3 overcurrent detect v oc 45 47.5 50 mv 1, 4 short circuit detect i sc 5.0 8.0 11 a 3 short circuit detect v sc 150 200 250 mv 1 overvoltage delay t ovd 0.8 1 1.2 sec undervoltage delay t uvd 90 100 110 ms overcurrent delay t ocd 5 10 20 ms short circuit delay t scd 80 100 120 s test threshold v tp 0.5 1.0 1.5 v test current i tst 10 20 40 a recovery charge current i rc 0.5 1 2 ma 13 downloaded from: http:///
ds2760 24 electrical characteristics: temperature, voltage, current (0 c to +50 c; 2.5v v dd 5.5v) parameter symbol min typ max units notes temperature resolution t lsb 0.125 c temperature full scale magnitude t fs 127 c temperature error t err 3 c 5 voltage resolution v lsb 4.88 mv voltage full scale magnitude v fs 4.75 v voltage offset error v oerr 1 lsb 6 voltage gain error v gerr 5 %v reading current resolution i lsb 0.625 15.625 ma v 3 4 current full scale magnitude i fs 1.9 2.56 64 a mv 3, 7 4 current offset error i oerr 1 lsb 8 current gain error i gerr 3 1 %i reading 3, 9, 14 4 accumulated current resolution q ca 0.25 6.25 mahr vhr 3 4 current sampling frequency f samp 1456 hz internal timebase accuracy t err 1 3 % 10 downloaded from: http:///
ds2760 25 electrical characteristics: 1-wire interface (-20 c to +70 c; 2.5v v dd 5.5v) parameter symbol min typ max units notes time slot t slot 60 120 s recovery time t rec 1 s write 0 low time t low0 60 120 s write 1 low time t low1 1 15 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 960 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s swap timing pulse width t swl 0.2 120 s swap timing pulse falling edge to dc release t swoff 0 1 s 12 swap timing pulse rising edge to dc engage t swon 0 1 s 12 dq capacitance c dq 60 pf eeprom reliability specification (-20 c to +70 c; 2.5v v dd 5.5v) parameter symbol min typ max units notes copy to eeprom time t eec 2 10 ms eeprom copy endurance n eec 25000 cycles 11 notes 1) all voltages are referenced to vss. 2) see ordering information section of datasheet to determine corresponding part number for each v ov value. 3) internal current sense resistor configuration. 4) external current sense resistor configuration. 5) self heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions. 6) voltage offset measurement is with respect to v ov at +25c. 7) the current register supports measurement magnitudes up to 2.56a using the intern al sense resistor option and 64mv with the external resistor option. compensation of the internal sense resistor value for process and temperature variation can reduce the maximum reportable magnitude to 1.9a. 8) current offset error null to 1lsb typically requires 3.5s in-system calibration by user. 9) current gain error specification applies to gain error in converting the voltage difference at is 1 and is2, and excludes any error remaining after the ds2760 compensates for the internal sense resistors tem perature coefficient of 3700ppm/ c to an accuracy of 500ppm/ c. the ds2760 does not compensate for external sense resistor characteristics, and any error terms arising from the use of an external sense resistor should be taken into account when calculating total current measurement error. 10) typical value for t err is at 3.6v and +25 c. 11) 4-year data retention at +70 c. 12) typical load capacitance on dc and cc is 1000pf. 13) test conditions are pls = 4.1v, v dd = 2.5v. maximum current for conditions of pls = 15v, v dd =0v is 10ma. 14) error at time of shipment from dallas semiconductor is 3% max. board mounting processes may cause the current gain error to widen to as much as 10% for devices with the internal sense resistor option. con tact factory for on-board recalibration procedure for devices with the inte rnal sense resistor option to improve accuracy. downloaded from: http:///

▲Up To Search▲

Price & Availability of DS2760AE-025

	To Download DS2760AE-025 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .